1. Field of the Invention
The present invention generally relates to a time base correction apparatus, and more particularly to an apparatus for correcting a time base error of a video signal.
2. Description of Background Information
Time base error is commonly generated in a video signal reproduced by a recorded information reproducing apparatus such as a video disc player or a video tape (or video cassette) recorder (VTR or VCR), which time base error is generated, for example, by a fluctuation of rotation in the mechanical system of the apparatus. Since the time base error is a cause of disturbances such as fluctuation of the picture and color blur or color variation, it is necessary to eliminate or reduce the time base error to as small an amount as possible in the video signal processing circuit.
On the other hand, a video signal reproducing system has been proposed by the applicants of the present application (reference is directed to Japanese Patent Application Laid Open No. 62-140587) in which the reproduced video signal is processed totally in digital form. A conventional time base correction apparatus in this video signal reproducing system will be specifically discussed with reference to FIG. 1.
As illustrated, an FM video signal read-out from a recording medium such as a video disc is supplied to an A/D converter 2 through an analog LPF (low pass filter) 1. The LPF 1 is provided for preventing the generation of aliasing distortion during the A/D conversion. The digitized FM video signal outputted from the A/D converter 2 is supplied to an RF processing circuit 7. This RF processing circuit 7 is comprised of a digital BPF (band pass filter) 3 for extracting only a component required for the detection of the video signal from the output signal of the A/D converter including the FM audio signal, a digital FM detector circuit 4 for FM detection of the extracted component, a video LPF 5 for extracting a base band component of the video signal from the detected output signal of the FM detector circuit 4, and a drop-out detection circuit 6 for detecting the drop-out of the video signal. The digitized video signal passed through the video LPF 5 is supplied to the drop-out correction circuit 8 and a PLL (phase locked loop) circuit 9.
The drop-out correction circuit 8 performs the correction of drop-outs in response to the drop-out detection signal supplied from the drop-out detection circuit 6. On the other hand, the PLL circuit 9 generates a master clock signal fM having a frequency of 4N.sub.1 fsc (N.sub.1 is an integer equal to or larger than 2, 4 for example, and fsc is the frequency of a color subcarrier signal) and synchronized with the digitized video signal supplied from the video LPF 5. The master clock fM is used as a sampling clock for the A/D converter 2, and as the clock signal for digital signal processing up to the video LPF 5. A divide by N.sub.1 circuit 10 is provided for dividing the master clock by N.sub.1, generating a clock signal WCK having a frequency of 4 fsc, and the clock WCK is used as the clock signal for the down sampling in the video LPF 5, and used as the sampling clock signal for the drop-out correction circuit 8.
The digitized video signal outputted from the drop-out correction circuit 8 is written into a buffer memory 12 by using the clock WCK. The read-out of data from the buffer memory 12 is performed by using a reference clock RCK having a frequency of 4 fsc generated by a reference clock signal generating circuit 11. The digitized video signal read out from the buffer memory 12 is converted to an analog form a by D/A converter 13, and outputted as a reproduced video signal.
FIG. 2 specifically shows an example of the PLL circuit 9. As shown, the playback horizontal sync signal (PBH) and the color burst signal (CB) are separated from the reproduced video signal by a signal separation circuit 21. As shown, the playback horizontal sync signal is supplied to a phase comparator 22 and the color burst signal is supplied to a phase comparator 24. A comparison output of the phase comparator 22 is supplied to a PLL control circuit 20 and also to a selector 23 as one of its two input signals. On the other hand, a comparison output of the phase comparator 24 is supplied to the PLL controller 20 and also to the selector 23 as the other one of the input signals thereof. The switching operation of the selector 23 is controlled by the PLL control circuit 20. The selection output signal of the selector 23 is supplied to a loop filter 25 for determining the loop characteristic of the PLL circuit. The loop filter 25 is a digital filter constructed to realize a desired characteristic, and its output is converted to an analog signal by a D/A converter 26, and in turn used as a control voltage for a VCO (voltage controlled oscillator) 27.
The oscillation frequency of the VCO 27 is controlled by the output voltage of the D/A converter 26, and its output signal becomes the master clock fM described before, and supplied to a divide by N.sub.2 circuit 28, and a divide by N.sub.3 circuit 29. The output signal of the divide by N.sub.2 circuit 28 is supplied to the phase comparator 22 as the other one of its input signals, and the output signal of the divide by N.sub.3 circuit 29 is supplied to the phase comparator 24 as the other one of its input signals. The PLL circuit is constructed by the circuit elements described above.
The divide by N.sub.2 circuit 28 is provided for dividing the output signal f.sub.M of the VCO 27 to produce the horizontal scanning frequency f.sub.H. Since f.sub.M =4N.sub.1 fsc, then N.sub.2 =910N.sub.1 in the NTSC system. On the other hand, the divide by N.sub.3 circuit is provided for dividing the output signal f.sub.M of the VCO 27 to produce the color subcarrier frequency fsc, hence N.sub.3 =4N.sub.1. The PLL control circuit 20 is constituted by a combination of flip-flop circuits and PLAs (programmable logic arrays), or by a microcomputer, and performs operations, such as switching the selector 23, resetting the loop filter 25 in the initial state, or resetting the dividing circuits 28 and 29.
In the PLL circuit 9 constructed as described above, the selector 23 is controlled to select the output signal (a) of the phase comparator 22 in the initial state or a non-steady state where the video signal is not reproduced in a stable manner, thereby the PLL circuit performs synchronization locking to the horizontal sync signal. When the PLL circuit is synchronized with the playback horizontal sync signal and it is in the steady state, the selector 23 is operated to select the output signal (b) of the phase comparator 24, thereby the PLL circuit performs the pull-in of synchronism to the color burst signal.
When the video signal is stably reproduced in the steady state, the PLL circuit is synchronized with the color burst signal with the selector 23 operated to select the output signal (b) of the phase comparator 24. However, if the synchronization of the PLL circuit is lost or placed in the non-steady state, the selector 23 is switched to select the output signal (a), so that the operation of the PLL circuit is returned to the state of the pull-in of synchronism to the playback horizontal sync signal. Subsequently, the PLL circuit returns to the operations described above. The PLL control circuit 20 is operative to switch the position of the selector by judging the state of synchronization or the loss of synchronization, and reset the divide by N.sub.2 circuit 28 when the selector 23 is switched to the position of selecting the output signal (a), and reset the divide by N.sub.3 circuit 29 when the selector 23 is switched to the position of selecting the output signal (b) so that the initial phase error is maintained as the smallest possible.
The phase comparators 22 and 24 operate as the time base error detection means, and the phase error signals outputted from these phase comparators are the time base error signals. Thus the PLL circuit is synchronized so that the phase error becomes equal to 0.
FIG. 3 is a block diagram showing an example of the construction of the phase comparator circuit 24 in FIG. 2 though it is different from the circuit described in Japanese Patent Application Laid Open No. 62-140587. In this figure, an adding and subtracting circuit 30 which receives the color burst signal (CB) as one of its input signals performs addition or subtraction in accordance with the signal logic ("H" or "L") of the color subcarrier frequency fsc. An addition or subtraction output signal of this adding and subtracting circuit 30 is fed into the first register 31 consisting of a D-flipflop during the color burst period in accordance with a clock signal having a frequency of 4 fsc outputted from the PLL control circuit 20. The output signal of the first register 31 is fed into a second register 32 consisting of a D-flipflop every time of reception of a clock which is the same as the clock of the first register 31 itself. The first and second registers 31 and 32 constitute a shift register, and the content of each register is reset to "0" , before the clock is inputted, by a reset signal outputted from the PLL controller 20 . The output signal of the first register 31 is outputted as the .SIGMA.A cos .theta. signal, and supplied as, one of the input signals, to a divider 33. On the other hand, the output signal of the second register 32 is outputted as the .SIGMA.A sin .theta. signal and is inputted to the adding and subtracting circuit 30 and the divider 33 as the other one of the input signals respectively. The output signal of the divider 33 represents the phase error .theta., after passing through a tan.sup.-1 converter 34 which is constituted by a ROM.
The color burst signal constituting one of the input signals of the adding and subtracting circuit 30 is illustrated in FIG. 4. Since the sampling frequency is 4 fsc, there are four sampling points in one cycle of the color burst signal. For explanatory purposes, these four sampling points are designated as S.sub.1, S.sub.2, S.sub.3, and S.sub.4 in order from the leading edge of the signal of color subcarrier frequency fsc.
With this configuration, the contents of the first and second registers 31 and 32 are reset to "0" by the reset signal from the PLL control circuit 20, before the calculation of the phase error. When the first sampled value S.sub.1 is inputted after the reset signal is removed, the output signal of the adding and subtracting circuit 30 becomes equal to S.sub.1 since the signal of color subcarrier frequency fsc is at the "H" level. This signal is fed into the register 31 at the first leading edge of the clock signal. Because the content of the register 31 is shifted to the register 32 at this time, the content of the register 32 remains as "0". When the sampled value S.sub.2 is inputted, the output signal of the adding and subtracting circuit 30 become equal to S.sub.2 since the signal of the color subcarrier frequency fsc has the "H" level. This signal is fed into the register 31 at the second leading edge of the clock signal, and the signal S.sub.1 shifted from the register 31 is fed into the register 32 at the same time. When the sampled value S.sub.3 is inputted, the output signal of the adding and subtracting circuit 30 becomes equal to S.sub.1 -S.sub.3 since the signal of color subcarrier frequency fsc has turned to the "L" level. This signal is fed into the register 31 at the third leading edge of the clock signal, and the signal S.sub.2 is fed into the register 32. When the sampled value S.sub.4 is inputted, the output signal of the adding and subtracting circuit becomes equal to S.sub.2 -S.sub.4 because the signal of color subcarrier frequency fsc has the "L" level. This signal is fed into the register 31 at the fourth leading edge of the clock signal and the signal of S.sub.1 -S.sub.3 is fed into the register 32.
As described above, the output signal of the adding and subtracting circuit 30 changes from S.sub.1 to S.sub.2, S.sub.1 -S.sub.3, S.sub.2 -S.sub.4, S.sub.1 +S.sub.1 -S.sub.3 in order, as the sampled value of the color burst signal is inputted in the order of S.sub.1, S.sub.2, S.sub.3, S.sub.4, S.sub.1, . . . . In this way, the first and second registers 31 and 32 the values of .SIGMA.(S.sub.2 -S.sub.4) and .SIGMA.(S.sub.1 -S.sub.3) while shifting the contents cyclically. If the phase difference between the color burst signal and the signal of color subcarrier frequency and the amplitude of the color burst signal are respectively represented by .theta. and A, the sampled values S.sub.1, S.sub.2, S.sub.3, and S.sub.4 respectively become A sin .theta., A cos .theta., -A sin .theta., -A cos .theta. when the color burst period has ended and the clock signal is stopped. Therefore, at that time the output signal of the first register becomes .SIGMA.(S.sub.2 -S.sub.4)+.SIGMA.A cos .theta., and the output of the second register 32 becomes .SIGMA.(S.sub.1 -S.sub.3)=.SIGMA.A sin .theta.. Thus, the output signal of the divider 33 becomes equal to tan .theta., and the phase error .theta. is obtained as the output signal of the tan.sup.-1 converter 34.
As explained with reference to FIG. 1, the reproduced video signal is written into the buffer memory by using a clock signal which follows the jitter of the reproduced video signal, and the read-out of data from the buffer memory 12 is performed by using the stable reference clock which does not follow the jitter of the reproduced video signal. The jitter component of the reproduced video signal is absorbed in this way. The phase error of the PLL circuit through the above operation is a residual time base error. Specifically, if the open loop gain of the PLL circuit is expressed by G, the reduction of the time base error is expressed by 1/(1+G).
However, with the feedback loop using the PLL circuit as explained above, the frequency bandwidth of the loop is limited by a period of phase comparison T=1/fH (fH is a horizontal scanning frequency, equal to 15.734 KHz), so that the open loop gain decreases as the signal frequency goes up. This means that the performance of elimination becomes lower for high frequency components (higher than 1 KHz) of the time base error. If it is attempted to increase the open loop gain at around the frequency of 1 KHz, then the phase margin decreases, and, in the closed loop gain characteristic, a peak will be generated in a frequency range higher than 2 or 3 KHz. In the frequency range higher than 2 or 3 KHz, the real time base error component is rather small and, instead, noises contained in the video signal and the error component of the phase comparator are relatively large.
Therefore, the peak in the closed loop characteristic causes increase in these noises and errors, and it causes an increase in the time base error as a result.
On the other hand, it is possible to improve the overall correction characteristic by using a time base error correction by the feedforward operation at the same time. However, the improvement of the elimination of time base error in high frequencies can not be expected unless the control signal for the feedforward correction and the video signal are synchronized in phase with each other.
On the other hand, in the case of digital time base correctors of conventional VTRs using magnetic tape of 1 inch wide, a clock following the time base error is generated by using the PLL circuit, and a clock dividing circuit is reset in phase by the feedforward control operation. Then the output of the clock dividing circuit is modulated in phase by an analog method so that the residual time base error is reduced, and the output is used as the clock signal for the A/D conversion and as the writing clock signal. However, since phase resetting and phase modulation in the generation of the writing clock signal are performed before the A/D conversion, the PLL circuit including the signal separating circuit and the time base error detection circuit is constituted by analog circuits. Furthermore, the signal whose time base error is removed and written into the memory is only the picture signal portion after the color burst signal. Therefore, this kind of method can not be used in the case of totally digital processes applied from processing the RF signal. This means that separately generated sync signals and color burst signal must be added to the signal read out from the memory. Furthermore, a time base correction method in which the memory read-out clock is controlled in phase by using the time base error is sometimes used in combination. However, this type of correction is only effective after D/A conversion of the video signal, and is not suited for the case where signal processing is performed in the form of the digital video signal in a later stage.